1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory) having so-called cylinder shaped capacitive electrodes whose lower electrodes are cylindrical, and a manufacturing method and a mask data preparing method for the same.
2. Background of the Invention
FIG. 1 is a sectional view showing the structure of a prior-art DRAM having cylindrical capacitive electrodes. At the surface of the semiconductor substrate, a first electric conductive impurity range 1 is formed, and diffusion layer 2 is formed within the impurity range 1. Furthermore, above the impurity range 1 and diffusion layer 2, gate electrode 3 and gate electrodes 4 are formed, and furthermore, on the entire surface, interlayer insulation film 5 is formed. On this interlayer insulation film 5, wiring layer 6 is formed. In the peripheral range of the DRAM, contacts 7 each having a great aspect ratio are formed within the interlayer insulation film 5, and by these contacts 7, connections between the impurity range 1 and wiring layer 6 and between the gate electrode 3 and wiring layer 6 are made. Also, metal barriers 8 are formed at the side surfaces and bottom surfaces of the contacts 7.
On the other hand, in the DRAM range, lower electrodes 10 each having a bottom and a cylindrical shape are formed so as to be embedded within the interlayer insulation film 5, and at the inner surfaces of the lower electrodes 10, thin capacitive insulating films 11 are formed. Furthermore, upper electrodes 12 are formed so as to fill the inside of the lower electrodes, and upper electrodes 12 extend in parallel to the substrate surface to form extending parts 13 of the upper electrodes. The bottom surfaces of the lower electrodes and impurity range 1 are connected by contacts 25, and at both sides of each contact 25, gate electrodes 4 are formed. Thereby, cylindrical capacitive cells are formed of the upper electrodes 12, capacitive insulating films 11, and lower electrodes 10.
And, between a pair of capacitive cells in the DRAM range, contact 20 is disposed. This contact 20 penetrates the interlayer insulation film 5 in the direction of the thickness, and electrically connects the upper wiring layer 6 and the impurity range 1 on the substrate. Also, at the side surface of the contact 20, metal barrier 21 is formed.
Also, between extending part 13 of the upper electrode 12 and the upper wiring layer 6, contact 22 is formed, and metal barrier 23 is also formed at the side surface of this contact 22. These contacts 20 and 22 are formed by embedding Cu metal plugs 20b and 22b into contact holes 20a and 22a after the contact holes 20a and 22a are etched in the interlayer insulation film 5.
In the prior-art DRAM memory device arranged as mentioned above, the wiring layer 6 connected to the contact 20 functions as a bit line, and the gate electrode 4 functions as a word line. And, in a condition where the bit line is selected, when the word line (gate electrode 4) of one of the two capacitive cells is caused to become high, an electrical charge is extracted from the capacitive cell, whereby the data is read.
FIG. 2 is a sectional view showing the structure of another prior-art DRAM having cylindrical capacitive electrodes. In FIG. 2, the same components as in FIG. 1 are attached with the same symbols, and detailed description thereof is omitted. As shown in FIG. 2, in this prior-art, side wall insulating films 26 are formed at the side surfaces of the contacts 20, 22, and 25. The prior-art DRAM shown in FIG. 1 has a problem in that a short circuit easily occurs between the contact 20 and extending part 13 extending sideward from the upper electrode 12. Therefore, in the prior-art shown in FIG. 2, by providing side wall insulating film 26 at the side surfaces of the contact, a short circuit between the contact and the other electric conductive portion is prevented.
However, due to this arrangement, in the prior-art shown in FIG. 2, contact between the upper electrode 12 (extending part 13) and contact 22 cannot be made at the side surface of the contact 22. Therefore, in this prior-art, a groove similar to the capacitive cell is formed in the interlayer insulating film 5 immediately under the upper electrode contact 22, and at the same time when forming the lower electrode 10, the same electric conductive substance is inserted and adhered into this groove to form electric conductive layer 27, and furthermore, at the same time when forming the upper electrode 12, the same electric conductive substance is inserted and adhered to form electric conductive layer 28, whereby the electric conductive substance is embedded and filled into the groove. Thereby, electrical contacts between the bottom surface of the contact 22 and electric conductive layers 27 and 28 are made.
Also, conventionally, the capacitive cells are disposed at a high density and high integration degree, and around these capacitive cells, contacts to be connected to the upper wiring extending from the upper electrode are provided. Such a designing of a mask for the contacts of the upper electrode extending parts is automatically made by using a CAD tool by taking the lower layer and surrounding layout margins into account, and mask data is generated. In this case, the contact positions can be determined only by providing margins so as to prevent short circuits between said contacts and the surrounding capacitive cells, other wiring, and contacts.
However, the above-mentioned prior-art DRAM memory device has the following defects. That is, in both memory devices of FIG. 1 and FIG. 2, the contacts 20 to draw the potentials of the lower electrodes 10 to the outside and the contacts 22 to draw the potentials of the upper electrodes 12 to the outside are different in aspect ratio from each other. Therefore, at the contacts 22, penetration due to etching occurs, or control of the film thickness of the metal barriers 24 to be formed at the bottom of the contact holes becomes difficult.
FIG. 3 is a graph wherein the horizontal axis shows aspect ratios,and the vertical axis shows etching rates, which shows the relationship between the etching rates and aspect ratios of the SiO2 film and polysilicon film, and the relationship between the SiO2/polysilicon selecting ratios and aspect ratios. The extending part 13 of the upper electrode 12 is normally formed from polysilicon, and the thickness thereof is approximately 1000 xc3x85, and the interlayer insulation film 5 is normally formed from SiO2, and thickness thereof is approximately 3 xcexcm. Also, the aspect ratio of the upper electrode contact 22 is approximately 1, and the aspect ratio of the lower electrode contact 20 is approximately 10. Then, as clearly understood from FIG. 3, if the contact holes 20a and 20b are formed in the same process, due to the difference in etching rate between them, both contact holes 20a and 22a are completed in about 4 minutes.
However, even if the etching selecting ratios differ, in the prior-art DRAM, since the aspect ratio is greatly different between the contact 20 and contact 22, in a case where the contact hole 20a and contact hole 22a are formed in the same etching process, the contact hole 22a may penetrate the extending part 13 of the upper electrode 12 as shown in FIG. 1. If so, as shown in FIG. 2, when side wall insulating film 26 is formed at the side surface of the contact hole 22a, electrical contact cannot be made with the extending part at the side surface of the contact 22. Therefore, as shown in FIG. 2, electric conductive layers 27 and 28 must be formed at the lower part of the contact 22.
Also, after the contact holes 20a and 22a are formed by means of etching, metal barriers 21 and 23 are formed at the inner surfaces thereof, however, since the aspect ratio greatly differs between the contact holes 20a and 22a, the film thicknesses of the metal barriers formed in the inner surfaces of the holes are difficult to control, and as shown in FIG. 1, at the contact 22, a thick metal barrier 24 may be formed at the bottom. If so, even when the bottom surface of the contact hole 22 is within the extending part 13, contact resistance between the contact 22 and extending part 13 greatly changes, whereby stable contact resistance cannot be obtained. Also, in the case of the contact 22 having the side wall insulating film 26 shown in FIG. 2, since it can be electrically contacted with the extending part 13 at the bottom section, it is a certain that the thick metal barrier 24 at the bottom of the contact cause unstable contact resistance.
It is an object of the present invention to provide a reliable semiconductor memory device and a manufacturing method for the same whereby unstable contact resistance and the penetration of the contact hole in the memory cell having a so-called cylinder shape can be prevented.
The semiconductor memory device according to the present invention comprises an interlayer insulation film, cylindrical lower electrodes formed within the interlayer insulation film, capacitive insulating films formed at the inner surfaces of the lower electrodes, upper electrodes formed so as to oppose the lower electrodes which sandwich the capacitive insulating films, cylindrical grooves formed within the interlayer insulation film, electric conductive layers formed at the inner surfaces of the grooves, upper electrode extending parts connecting the upper electrodes and electric conductive layers, upper electrode contacts formed at the interlayer insulation film and connected to the electric conductive layers at the bottom of the grooves, and upper electrode wiring formed on the interlayer insulation film and connected to the upper electrode contacts.
Another semiconductor memory device according to the present invention comprises a semiconductor substrate, a diffusion layer formed on the surface of the semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate, cylindrical lower electrodes formed within the interlayer insulation film and connected to the diffusion layer, capacitive insulating films formed at the inner surfaces of the lower electrodes, upper electrodes formed so as to oppose the lower electrodes by sandwiching the capacitive insulating films, cylindrical grooves formed within the interlayer insulation film, electric conductive layers formed at the inner surfaces of the grooves, upper electrode extending parts connecting the upper electrodes and electric conductive layers, upper electrode contacts formed at the interlayer insulation film and connected to the electric conductive layers at the bottom of the grooves, upper electrode wiring formed on the interlayer insulation film and connected tot he upper electrode contacts, and a peripheral contact formed within the interlayer insulation film and connected tot he diffusion layer.
This semiconductor memory device can be arranged so as to comprise the lower electrode contacts formed so as to penetrate the interlayer insulation film, word line gate electrodes provided between the connection parts of the lower electrodes and lower electrode contacts on the surface of the diffusion layer, and lower electrode wiring formed on the interlayer insulation film and connected to the lower electrode contacts, or can be arranged so as to comprise lower electrode wiring formed lower than the lower electrodes in the interlayer insulation film, and lower electrode contacts formed at the interlayer insulation film to connect the lower electrode wiring and diffusion layer.
Also, side wall insulating films are formed at the side surfaces of the upper electrode contacts and lower electrode contacts, and at the bottom surfaces and side surfaces of the upper electrode contacts and lower electrode contacts, metal barrier layers are formed.
The manufacturing method for semiconductor memory device according to the present invention comprises the steps of forming a diffusion layer and gate electrode on the surface of a semiconductor substrate, forming an interlayer insulation film on the surface of the semiconductor substrate, simultaneously forming capacitive cell grooves and upper electrode contact grooves in the interlayer insulation film forming electric conductive substances on the bottom surfaces and side surfaces of the capacitive cell grooves and upper electrode contact grooves to form lower electrodes and a first electric conductive layer, forming capacitive insulating films on the inner side surfaces and bottom surfaces of the lower electrodes of the capacitive cell grooves forming electric conductive substances in the capacitive cell grooves and upper electrode contact grooves to form upper electrodes and a second electric conductive layer, and simultaneously forming upper electrode extending parts connecting the upper electrodes and second electric conductive layer, embedding insulation substances in the upper electrode contact grooves, simultaneously forming upper electrode contact holes and lower electrode contact holes at the insulation substances in the upper electrode contact grooves and interlayer insulation film, and embedding electric conductive substances in the upper electrode contact holes and lower electrode contact holes to form upper electrode contacts and lower electrode contacts.
Another manufacturing method for a semiconductor memory device according to present invention comprises the steps of forming a diffusion layer and gate electrodes on the surface of a semiconductor substrate, forming a first interlayer insulation film on the surface of the semiconductor substrate, forming lower electrode contacts at the first interlayer insulation film, and forming upper electrode wiring on the first interlayer insulation film, forming a second interlayer insulation film on the first interlayer insulation film, simultaneously forming capacitive cell groove and upper electrode contact grooves in the second interlayer insulation film, forming electric conductive substances at the bottom surfaces and side surfaces of the capacitive cell grooves and upper electrode contact grooves to form lower electrodes and a first electric conductive layer, forming capacitive insulating films on the inner surfaces and bottom surfaces of the lower electrodes of the capacitive cell grooves, embedding electric conductive substances into the capacitive cell grooves to form upper electrodes, forming electric conductive substances in the upper electrode contact grooves to form a second electric conductive layer, and simultaneously forming upper electrode extending parts connecting the upper electrodes and the second electric conductive layer, embedding insulation substances into the upper electrode contact grooves, forming upper electrode contact holes in the insulation substances in the upper electrode contact grooves, and embedding electric conductive substances into the upper electrode contact holes to form upper electrode contacts.
In the mask data preparing method and layout method of a semiconductor memory device according to the present invention, by determining the product of the upper electrode contact data and upper electrode extending parts, a step for extracting only the upper electrode contact data formed on the upper electrode extending parts from the upper electrode contact data is carried out. Next, the extracted upper electrode contact data is added to groove data to prepare cylinder data of the upper electrode extending parts, and the increased data is disposed with a margin so as not to be contacted by the surrounding wiring.
The foregoing and other features and advantages of the present invention will become more readily more appreciated as the same becomes better understood by reference to the following detailed description when taken into conjunction with the accompanying drawings.